The Simple Bus Architecture (SBA) is an architecture made up software tools and intellectual property cores (IP Cores) interconnected by buses set through simple and clear rules, that allow the implementation of a system embedded on chip (SoC); additionally, basic templates are provided to achieve a rapid design. Its structure gives it an inherent educative value. The VHDL code that implements this architecture is highly portable.
The master core developed as a special state machine has the ability to perform basic data flow and processing, similar to microprocessor but without the high consumption of logic resources of it.
The SBA is an application and simplified version of the Wishbone specification. The SBA implements the minimum essential subset of Wishbone signals interface and can be easily connected with simple Wishbone IP Cores. The SBA defines three types of cores: masters, slaves, and auxiliaries. Several slaves IP Cores were developed following the SBA architecture, many of them to implement virtual instruments.
Article in Spanish about v1.0 version is here
The SBA also provides some files as bus configuration and functions package for easy define how the cores will be interconnected, how the data will travel into the buses and what addresses the slaves cores will have in the main address map.
SBA Basic Diagram
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